`timescale 1ns/1ps 

module tb_top(/*AUTOARG*/
   // Outputs
   out_valid1, out_valid0, float_data_out1, float_data_out0,
   float_data_movld, float_data_aovld, FP_MULTZ, FP_ADDZ
   );

/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0]		FP_ADDZ;		// From FPadd of FPadd.v
output [31:0]		FP_MULTZ;		// From FPmul of FPmul.v
output			float_data_aovld;	// From FPadd of FPadd.v
output			float_data_movld;	// From FPmul of FPmul.v
output [31:0]		float_data_out0;	// From u0_int2float of int2float.v
output [31:0]		float_data_out1;	// From u1_int2float of int2float.v
output			out_valid0;		// From u0_int2float of int2float.v
output			out_valid1;		// From u1_int2float of int2float.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire			clk;			// From u_clk_gen of clk_gen.v
wire [31:0]		float_data_a0;		// From tx_sys of tx_sys.v
wire [31:0]		float_data_a1;		// From tx_sys of tx_sys.v
wire			float_data_avld;	// From tx_sys of tx_sys.v
wire [31:0]		float_data_m0;		// From tx_sys of tx_sys.v
wire [31:0]		float_data_m1;		// From tx_sys of tx_sys.v
wire			float_data_mvld;	// From tx_sys of tx_sys.v
wire			in_valid0;		// From tx_sys of tx_sys.v
wire			in_valid1;		// From tx_sys of tx_sys.v
wire [31:0]		int_data_in0;		// From tx_sys of tx_sys.v
wire [31:0]		int_data_in1;		// From tx_sys of tx_sys.v
wire			rst_n;			// From u_rst_gen of rst_gen.v
// End of automatics

/*clk_gen AUTO_TEMPLATE(
      .ref_clk          		(clk) ,
     );*/

/*int2float  AUTO_TEMPLATE(
      .reset (~rst_n),
      .float_data_out	(float_data_out@[31:0]),
      .out_valid		(out_valid@),
      .int_data_in	(int_data_in@[31:0]),
      .in_valid		(in_valid@),
     );*/


/*FPadd  AUTO_TEMPLATE(
    .FP_A			(float_data_a0[31:0]),
    .FP_B			(float_data_a1[31:0]),
	    .FP_Z			(FP_ADDZ[31:0]),
	    .ADD_SUB			(1'd1),
	    .IVLD    (float_data_avld),
	    .OVLD    (float_data_aovld),

     );*/

    
/*FPmul  AUTO_TEMPLATE(
    .FP_A			(float_data_m0[31:0]),
    .FP_B			(float_data_m1[31:0]),
	    .FP_Z			(FP_MULTZ[31:0]),
	    .IVLD    (float_data_mvld),
	    .OVLD    (float_data_movld),
     );*/


int2float u0_int2float (/*AUTOINST*/
			// Outputs
			.float_data_out	(float_data_out0[31:0]), // Templated
			.out_valid	(out_valid0),		 // Templated
			// Inputs
			.clk		(clk),
			.reset		(~rst_n),		 // Templated
			.int_data_in	(int_data_in0[31:0]),	 // Templated
			.in_valid	(in_valid0));		 // Templated

int2float u1_int2float (/*AUTOINST*/
			// Outputs
			.float_data_out	(float_data_out1[31:0]), // Templated
			.out_valid	(out_valid1),		 // Templated
			// Inputs
			.clk		(clk),
			.reset		(~rst_n),		 // Templated
			.int_data_in	(int_data_in1[31:0]),	 // Templated
			.in_valid	(in_valid1));		 // Templated


FPadd FPadd(/*AUTOINST*/
	    // Outputs
	    .FP_Z			(FP_ADDZ[31:0]),	 // Templated
	    .OVLD			(float_data_aovld),	 // Templated
	    // Inputs
	    .ADD_SUB			(1'd1),			 // Templated
	    .FP_A			(float_data_a0[31:0]),	 // Templated
	    .FP_B			(float_data_a1[31:0]),	 // Templated
	    .clk			(clk),
	    .IVLD			(float_data_avld));	 // Templated
FPmul FPmul(/*AUTOINST*/
	    // Outputs
	    .FP_Z			(FP_MULTZ[31:0]),	 // Templated
	    .OVLD			(float_data_movld),	 // Templated
	    // Inputs
	    .FP_A			(float_data_m0[31:0]),	 // Templated
	    .FP_B			(float_data_m1[31:0]),	 // Templated
	    .clk			(clk),
	    .IVLD			(float_data_mvld));	 // Templated



rst_gen u_rst_gen(/*AUTOINST*/
		  // Outputs
		  .rst_n		(rst_n));
clk_gen u_clk_gen(/*AUTOINST*/
		  // Outputs
		  .ref_clk		(clk));			 // Templated
dump dump();
monitor monitor();
forcelist forcelist();

tx_sys  tx_sys(/*AUTOINST*/
	       // Outputs
	       .int_data_in0		(int_data_in0[31:0]),
	       .in_valid0		(in_valid0),
	       .int_data_in1		(int_data_in1[31:0]),
	       .in_valid1		(in_valid1),
	       .float_data_a0		(float_data_a0[31:0]),
	       .float_data_a1		(float_data_a1[31:0]),
	       .float_data_m0		(float_data_m0[31:0]),
	       .float_data_m1		(float_data_m1[31:0]),
	       .float_data_avld		(float_data_avld),
	       .float_data_mvld		(float_data_mvld),
	       // Inputs
	       .clk			(clk),
	       .rst_n			(rst_n));
endmodule




